Physical verification is very critical to the success of the chip design. One of the most important key steps to perform physical verification on the layout design is to verify that the layout matches the schematic. This is so called LVS (layout-versus-schematic), which involves checking the consistency between the original schematic netlist and the one extracted from the layout. Because of the design reuse and the implementation of the multiple power/ground domains, VDD (or VDD, both designating the positive power supply voltage in field effect transistors or unipolar transistors) and GND (ground) are designed as global nets, but they are not globally connected throughout the chip. The standard LVS flow, which verifies VDD and GND as global nets, may no longer be functional.
LVS is one of the most important physical verification steps in integrated circuit (IC) design. It serves to check the equivalency of a layout design against the corresponding schematic design. If the two designs are equivalent under the given LVS rule deck (LVS runset), then the LVS result is said to be “LVS clean”. LVS tools first generate a netlist based on extracting the connectivity of an input layout stream file. The extracted netlist is then compared to the schematic netlist to ensure the two views match.
Power nets are typically globally connected throughout the design, and so are the ground nets. VDD and GND are designed as global nets at the block level, which is done to simplify the schematic level design process; treating them as local nets would require creating specific hierarchical ports for VDD and GND within each schematic. At the full-chip level, however, under the multiple power/ground domains scenario VDD and GND can no longer be treated as global nets. LVS methodology for the block level now fails at the full-chip level. For example, a short on GND between different processor cores cannot be detected because GND is considered to be global. The design team needed an LVS methodology that enabled each block to be independently verified during the development. They also needed the LVS flow to be capable of verifying the integrity of the chip level power grid with minimum impact in altering the design.
In hierarchical LVS, layout text is viewed hierarchically. In a schematic netlist, nets listed as global are assumed to be connected throughout the design during netlist comparison. Similarly, nets defined as global in layout are treated as global during netlist extraction. Global net names are dispersed through connections up the hierarchy. Local or non-global nets only specify a net's value for a particular hierarchical level. If two or more texts are attached to one net, LVS reports this as a short. A text open is reported, if different physical nets have the same text.
Multi-power-domain LVS is the second phase of the LVS flow, which targets verifying the integrity of the chip-level power grid. Unlike the standard-LVS, in which VDD and GND are treated as global names, multi-power-domain LVS analyzes power and ground nets as local nets. A netlist parser is implemented to create a schematic netlist with localized VDD and GND nets, and also the multipower-domain power and ground names are added as ports at the appropriate level of netlist hierarchy based on the information provided in a configuration file. The actual multi-power-domain power and ground names labeled at the bumps are used in the second phase LVS. Hence, any opens or shorts on the power-grid will be reported upon completing the multi-power-domain LVS verification.
In the design of integrated circuits, saving power has become one of the primary goals, and designers are usually forced to use sophisticated techniques such as clock gating, multi-voltage logic, and turning off the power entirely to inactive blocks. Recent development in power-saving techniques have resulted in the Si2 Common Power Format (CPF) and subsequently the IEEE Unified Power Format (UPF), both of which are file formats for specifying power-saving techniques early in the design process. These techniques require a consistent implementation in the design steps of logic design, implementation, and verification.
For example, if multiple different power supplies are used, then logic synthesis must insert level shifters, place and route must deal with them correctly, and other tools such as static timing analysis (STA) and formal verification must understand these components. As power became an increasingly pressing concern, each tool independently added the features needed. Although this makes it possible to build low power flows, it was difficult and error prone since the same information needed to be specified several times, in several formats, to many different tools. CPF and UPF were created as common formats that many tools can use to specify power-specific data, so that power intent only need be entered once and can be used consistently by all tools. The aim of CPF and UPF is to support an automated, power-aware design infrastructure, and a CPF or an UPF power connection expects power and ground terminals within an instantiated components.
Another challenge in electronic design occurs when transistor level netlist of the components instantiated within a digital or mixed-signal block do not have power and ground terminals, but rather have some global signal decorated with a special property placed on a net or terminal to define its connectivity, while the power connectivity of the digital or mixed-signal block is described by, for example, a CPF or an UPF file. Such a special property may be, for example, a net expression or an oaNetConnectDef or oaTermConnectDef for OpenAccess (OA) by the OpenAccess Coalition (hereinafter a net/terminal expression or a net or terminal expression). The challenge arises when generating transistor netlist from the digital or mixed-signal block when trying to connect power and ground nets of the components transistor level netlists to the CPF or UPF based power and ground nets which have multiple power domains.
For example, the traditional approach outputs reference cell schematics with global power and ground nets (such as using a CDL (circuit description language)-out function in some EDA (electronic design automation) tools. This traditional approach then outputs the logical HDL model (such as a Verilog model), and then feeds the layout-versus-schematic (LVS) tool with the digital or mixed-signal block CDL netlist and layout. The issues with this traditional approach is that this traditional approach does not work if two instances of the same reference cell are to be connected to two different domains because these two instances would share the same CDL netlist with the same global power and ground nets.
Various approaches have been proposed to solve the aforementioned challenges. One of the approaches uses scripts to automatically add power and ground terminals to the reference cell schematics and then uses the RTL compiler or an RTL to GDSII tool to dump the physical HDL model (such as a Verilog model). This approach then uses, for example, a schematic editor to import the physical Verilog model and performs CDL-out. The drawbacks of this approach is that the reference cell schematics are often considered as golden and do not allow changes. Moreover, the addition of power and ground terminals to each reference cell schematic is cumbersome, especially for analog IP (intellectual property) schematics.
Another approach uses the RTL compiler or the RTL to GDSII tool to dump the physical Verilog model, and then uses scripts to translate the physical Verilog model into a Verilog (for example, a netSet-based or oaAssignment-based Verilog) based on one or more lookup properties or one or more overriding properties of one or more special properties that are placed on a net or terminal to define its connectivity. Hereinafter, the one or more lookup properties or one or more overriding properties of one or more special properties that are placed on one or more instances to define their connectivity (such as a netSet or an oaAssignment in OpenAccess by the OpenAccess Coalition) are collectively referred to as a net/terminal set for simplicity in this application, and the one or more special properties that are placed on a net or a terminal to define its connectivity (such as a netExpression, a terminalExpression, or an oaNetConnectDef or oaTermConnectDef for OpenAccess) are collectively referred to as a net/terminal expression or a net or terminal expression. Finally, the approach uses the schematic editor or other similar EDA tools to perform CDL-OUT.
Another approach performs CDL-OUT for all reference cell schematics with automatically drilled or placed power and ground terminals or pins and then uses, for example, a schematic editor to dump the physical Verilog. This approach finally translates the physical Verilog with another tool such as a Verilog2CDL. A similar approach uses scripts to post process the CDL to add power and ground terminals. All these approaches require manual addition of the power and ground terminals, modification of the reference cell schematics which are often golden and thus do not allow modification, do not consider the CPF or UPF files for specifying power-saving techniques in the early stages of the design.